The present invention relates generally to the field of I/O (input/output) adapter cards, and more particularly to the placement of I/O adapter cards.
Computer systems (such as blade servers) can be made to run more effectively and/or efficiently by “offloading” certain repetitive tasks to processing hardware other than the CPU (central processing unit). Certain hardware dedicated to perform these repetitive tasks is known as accelerator cards and/or adapter cards (collectively herein called cards). Cards are removably insertable from input/out (I/O) slots. Typically, these cards are used for encryption, compression, or custom algorithms and are placed in a PCI (peripheral component interconnect) or PCIe (peripheral component interconnect express) slot.
PCIe is a high-speed serial computer expansion bus standard. PCIe operates in consumer, server, and industrial applications, as: (i) a motherboard level interconnect (to link motherboard-mounted peripherals; (ii) a passive backplane interconnect; and (iii) as an expansion card interface for add-in boards. Differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors. New motherboards and new adapter boards are required for PCIe, and thus, PCI (peripheral component interconnect) slots and PCIe slots are not interchangeable. At the software level, PCIe preserves backward compatibility with PCI. Legacy PCI system software can detect and configure newer PCIe devices without explicit support for the PCIe standard, although PCIe's new features are inaccessible.
In a typical multi-socket processor server configuration, processors in both sockets offer PCIe slots where adapters or accelerator cards can be placed. However, based on the system configuration, each of the sockets may have different types of memory devices connected to them. Such multi-processor and multi-PCIe slot configurations are common when a server computer is built-to-order, and where the requirements for different types of memory devices are based on the read/write requirements of the workloads placed on the servers. Home node for the workload can be decided on: (i) based on the memory read/write heuristics of the workload; and/or (ii) by mapping the memory configuration associated with each processor.